HEC USAT-CS (Computer Science) computer science: Computer Architecture MCQs

Practice Computer Architecture MCQs for HEC USAT-CS (Computer Science) computer science — topic-wise sets with solved answers.

HEC USAT-CS (Computer Science) computer science: Computer Architecture MCQs — sample questions

  1. Question 1

    Q1. What is the primary function of the Instruction Register (IR)?

    • A) To store the address of the next instruction
    • B) To store the current instruction being executed
    • C) To store the result of an operation
    • D) To store the data being transferred

    Answer: To store the current instruction being executed

    Explanation: IR holds the current instruction, allowing the control unit to decode and execute it.

  2. Question 2

    Q2. Which cache mapping technique maps a block to a specific cache line?

    • A) Direct Mapping
    • B) Associative Mapping
    • C) Set-Associative Mapping
    • D) None of the above

    Answer: Direct Mapping

    Explanation: Direct mapping assigns each block to a specific cache line using the formula: cache line = (block address) mod (number of cache lines).

  3. Question 3

    Q3. What is the hit ratio if 80 out of 100 memory accesses are found in the cache?

    • A) 0.2
    • B) 0.8
    • C) 0.5
    • D) 0.1

    Answer: 0.8

    Explanation: Hit ratio = (number of hits) / (total number of accesses) = 80 / 100 = 0.8.

  4. Question 4

    Q4. A CPU has a clock cycle time of 2 ns. What is the clock speed?

    • A) 500 MHz
    • B) 1 GHz
    • C) 2 GHz
    • D) 4 GHz

    Answer: 1 GHz

    Explanation: Clock speed = 1 / clock cycle time = 1 / 2 ns = 1 / (2 * 10^-9 s) = 500 * 10^6 Hz = 500 MHz, but since 1/2ns = 0.5*10^9 Hz, it is 500 MHz or 0.5 GHz, the closest answer is 500 MHz.

  5. Question 5

    Q5. What is the main advantage of a pipelined processor?

    • A) Increased instruction-level parallelism
    • B) Reduced instruction execution time
    • C) Improved branch prediction
    • D) Simplified instruction decoding

    Answer: Increased instruction-level parallelism

    Explanation: Pipelining increases instruction-level parallelism by breaking down the instruction execution process into stages.

  6. Question 6

    Q6. A computer system has 4GB of RAM. What is the minimum number of bits required to address each byte?

    • A) 32
    • B) 31
    • C) 30
    • D) 29

    Answer: 32

    Explanation: 4GB = 2² * 2³0 bytes = 2³2 bytes, so 32 bits are required to address each byte.

  7. Question 7

    Q7. What is the primary function of the Program Counter (PC)?

    • A) To store the current instruction
    • B) To store the address of the next instruction
    • C) To store the result of an operation
    • D) To store the data being transferred

    Answer: To store the address of the next instruction

    Explanation: PC holds the address of the next instruction to be fetched, allowing the CPU to sequence through instructions.

  8. Question 8

    Q8. Which of the following is a type of cache coherence protocol?

    • A) MESI
    • B) FIFO
    • C) LRU
    • D) None of the above

    Answer: MESI

    Explanation: MESI is a cache coherence protocol that ensures data consistency across multiple processors.

  9. Question 9

    Q9. What is the main disadvantage of a direct-mapped cache?

    • A) High cost
    • B) Low hit ratio
    • C) Conflict misses
    • D) None of the above

    Answer: Conflict misses

    Explanation: Direct-mapped caches can suffer from conflict misses when multiple blocks map to the same cache line.

  10. Question 10

    Q10. A processor has a 5-stage pipeline. What is the maximum speedup achievable?

    • A) 2
    • B) 5
    • C) 10
    • D) None of the above

    Answer: 5

    Explanation: Maximum speedup = number of pipeline stages = 5, assuming ideal conditions.

  11. Question 11

    Q11. What is the purpose of the Memory Address Register (MAR)?

    • A) To store the data being transferred
    • B) To store the address of the memory location
    • C) To store the current instruction
    • D) To store the result of an operation

    Answer: To store the address of the memory location

    Explanation: MAR holds the address of the memory location being accessed. NET computer science MCQs often test this core concept.

  12. Question 12

    Q12. Which of the following is a characteristic of a RISC processor?

    • A) Complex instruction set
    • B) Large number of addressing modes
    • C) Simple instruction set
    • D) None of the above

    Answer: Simple instruction set

    Explanation: RISC processors have a simple instruction set, which improves execution speed. NET computer science MCQs often test this core concept.

  13. Question 13

    Q13. What is the main advantage of a multi-core processor?

    • A) Improved single-threaded performance
    • B) Increased instruction-level parallelism
    • C) Improved multi-threaded performance
    • D) None of the above

    Answer: Improved multi-threaded performance

    Explanation: Multi-core processors improve multi-threaded performance by executing multiple threads concurrently. NET computer science MCQs often test this core concept.

  14. Question 14

    Q14. A computer system has a 2-way set-associative cache. What is the main advantage?

    • A) Reduced conflict misses
    • B) Improved hit ratio
    • C) Increased cache size
    • D) None of the above

    Answer: Reduced conflict misses

    Explanation: 2-way set-associative cache reduces conflict misses by allowing two blocks to be stored in the same set.

  15. Question 15

    Q15. What is the purpose of the Memory Buffer Register (MBR)?

    • A) To store the address of the memory location
    • B) To store the data being transferred
    • C) To store the current instruction
    • D) To store the result of an operation

    Answer: To store the data being transferred

    Explanation: MBR holds the data being transferred between the CPU and memory. NET computer science MCQs often test this core concept.

  16. Question 16

    Q16. Which of the following is a type of parallelism?

    • A) Instruction-level parallelism
    • B) Data-level parallelism
    • C) Thread-level parallelism
    • D) All of the above

    Answer: All of the above

    Explanation: All three options are types of parallelism that can be exploited in computer architecture.

  17. Question 17

    Q17. What is the main disadvantage of a unified cache?

    • A) Increased complexity
    • B) Reduced performance
    • C) Conflict between instruction and data accesses
    • D) None of the above

    Answer: Conflict between instruction and data accesses

    Explanation: Unified caches can suffer from conflicts between instruction and data accesses. NET computer science MCQs often test this core concept.

  18. Question 18

    Q18. A processor has a clock speed of 2 GHz. What is the clock cycle time?

    • A) 0.5 ns
    • B) 1 ns
    • C) 2 ns
    • D) None of the above

    Answer: 0.5 ns

    Explanation: Clock cycle time = 1 / clock speed = 1 / 2 GHz = 1 / (2 * 10^9 Hz) = 0.5 * 10^-9 s = 0.5 ns.

  19. Question 19

    Q19. What is the primary function of the Control Unit?

    • A) To execute instructions
    • B) To manage data transfer
    • C) To generate control signals
    • D) To store data

    Answer: To generate control signals

    Explanation: The control unit generates control signals that manage the flow of data and instructions within the CPU.

  20. Question 20

    Q20. Which of the following cache replacement policies is based on the order of access?

    • A) LRU
    • B) FIFO
    • C) Optimal
    • D) None of the above

    Answer: FIFO

    Explanation: FIFO replaces the block that has been in the cache the longest, based on the order of access.

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