PU CET Lahore (Engineering & CS) computer science Computer Architecture — Set 2

Computer Architecture MCQs set 2 for PU CET Lahore (Engineering & CS) computer science — 20 solved questions.

PU CET Lahore (Engineering & CS) computer science Computer Architecture — Set 2

  1. Question 1

    Q1. What is the primary function of the Instruction Register (IR) in the CPU?

    • A) To store the program counter
    • B) To store the current instruction being executed
    • C) To store the data being processed
    • D) To store the flags

    Answer: To store the current instruction being executed

    Explanation: IR holds the current instruction, decoding it for execution. It is a crucial register in the CPU's control unit.

  2. Question 2

    Q2. Which of the following cache mapping techniques uses a tag to identify the block?

    • A) Direct Mapping
    • B) Associative Mapping
    • C) Set-Associative Mapping
    • D) All of the above

    Answer: All of the above

    Explanation: All three mapping techniques use tags to identify blocks. Direct mapping uses a fixed location, while associative and set-associative use tags for flexibility.

  3. Question 3

    Q3. What is the hit ratio if a cache access takes 1 cycle, miss penalty is 5 cycles, and average memory access time is 2 cycles?

    • A) 0.25
    • B) 0.5
    • C) 0.75
    • D) 0.9

    Answer: 0.75

    Explanation: Using the formula: Average Access Time = Hit Ratio * Cache Access Time + (1 - Hit Ratio) * (Cache Access Time + Miss Penalty), we get 2 = Hit Ratio * 1 + (1 - Hit Ratio) * (1 + 5). Solving for Hit Ratio gives 0.75.

  4. Question 4

    Q4. In a 2-level memory hierarchy, the access time of the cache is 10 ns and that of the main memory is 100 ns. If the hit ratio is 0.8, what is the average access time?

    • A) 28 ns
    • B) 30 ns
    • C) 32 ns
    • D) 40 ns

    Answer: 28 ns

    Explanation: Average Access Time = Hit Ratio * Cache Access Time + (1 - Hit Ratio) * Main Memory Access Time = 0.8 * 10 + 0.2 * 100 = 8 + 20 = 28 ns.

  5. Question 5

    Q5. Which of the following is NOT a type of instruction-level parallelism?

    • A) Pipelining
    • B) Superscalar execution
    • C) VLIW
    • D) Multithreading

    Answer: Multithreading

    Explanation: Multithreading is a technique to improve utilization by switching between threads. It is not a type of instruction-level parallelism, which involves executing multiple instructions simultaneously.

  6. Question 6

    Q6. What is the main advantage of using a Harvard architecture over a von Neumann architecture?

    • A) Simplified instruction decoding
    • B) Faster execution due to separate instruction and data buses
    • C) Improved memory utilization
    • D) Reduced CPU complexity

    Answer: Faster execution due to separate instruction and data buses

    Explanation: Harvard architecture has separate buses for instructions and data, allowing for simultaneous access and improving overall system performance.

  7. Question 7

    Q7. In a pipelined processor, what is the primary function of the 'IF' stage?

    • A) Instruction Fetch
    • B) Instruction Decode
    • C) Execution
    • D) Memory Access

    Answer: Instruction Fetch

    Explanation: The 'IF' stage is responsible for fetching the next instruction from memory, which is then processed in subsequent stages.

  8. Question 8

    Q8. What is the purpose of the 'TLB' in a virtual memory system?

    • A) To cache frequently accessed instructions
    • B) To cache frequently accessed data
    • C) To cache page tables
    • D) To cache translation of virtual to physical addresses

    Answer: To cache translation of virtual to physical addresses

    Explanation: The Translation Lookaside Buffer (TLB) caches the translation of virtual to physical addresses, speeding up memory access.

  9. Question 9

    Q9. What is the main benefit of out-of-order execution in a processor?

    • A) Improved instruction-level parallelism
    • B) Simplified instruction decoding
    • C) Reduced power consumption
    • D) Increased cache hits

    Answer: Improved instruction-level parallelism

    Explanation: Out-of-order execution allows the processor to execute instructions as soon as their operands are available, improving overall instruction-level parallelism.

  10. Question 10

    Q10. Which of the following cache replacement policies is based on the least recently used block?

    • A) FIFO
    • B) LRU
    • C) Random
    • D) Optimal

    Answer: LRU

    Explanation: LRU (Least Recently Used) is a cache replacement policy that replaces the block that has not been accessed for the longest time.

  11. Question 11

    Q11. What is the primary function of the 'ID' stage in a pipelined processor?

    • A) Instruction Fetch
    • B) Instruction Decode
    • C) Execution
    • D) Memory Access

    Answer: Instruction Decode

    Explanation: The 'ID' stage is responsible for decoding the instruction, determining the operation to be performed, and fetching operands.

  12. Question 12

    Q12. In a virtual memory system, what is the purpose of the 'page table'?

    • A) To store the page frames in main memory
    • B) To store the mapping of virtual to physical addresses
    • C) To store the page replacement policy
    • D) To store the page fault handler

    Answer: To store the mapping of virtual to physical addresses

    Explanation: The page table stores the mapping of virtual pages to physical page frames, enabling the translation of virtual to physical addresses.

  13. Question 13

    Q13. What is the main advantage of using a multi-core processor?

    • A) Improved single-threaded performance
    • B) Increased instruction-level parallelism
    • C) Better multithreading support
    • D) Reduced power consumption

    Answer: Better multithreading support

    Explanation: Multi-core processors provide multiple processing cores, allowing for better support of multithreaded applications and improved overall system throughput.

  14. Question 14

    Q14. Which of the following is a characteristic of a CISC (Complex Instruction Set Computer) architecture?

    • A) Load/store architecture
    • B) Simple instruction set
    • C) Microcode-based instruction execution
    • D) Fixed-length instructions

    Answer: Microcode-based instruction execution

    Explanation: CISC architectures often use microcode to implement complex instructions, allowing for a wide range of operations to be performed in a single instruction.

  15. Question 15

    Q15. What is the purpose of the 'branch predictor' in a processor?

    • A) To predict the outcome of a branch instruction
    • B) To predict the target address of a branch instruction
    • C) To predict the instruction fetch sequence
    • D) To predict the data access pattern

    Answer: To predict the outcome of a branch instruction

    Explanation: The branch predictor predicts the outcome of a branch instruction (taken or not taken), allowing the processor to speculatively fetch instructions and improve overall performance.

  16. Question 16

    Q16. In a pipelined processor, what is the effect of a 'stall' or 'bubble'?

    • A) It increases the instruction-level parallelism
    • B) It reduces the instruction-level parallelism
    • C) It improves the branch prediction accuracy
    • D) It reduces the cache miss rate

    Answer: It reduces the instruction-level parallelism

    Explanation: A stall or bubble in a pipelined processor introduces a delay, reducing the instruction-level parallelism and overall system performance.

  17. Question 17

    Q17. What is the primary function of the 'MEM' stage in a pipelined processor?

    • A) Instruction Fetch
    • B) Instruction Decode
    • C) Execution
    • D) Memory Access

    Answer: Memory Access

    Explanation: The 'MEM' stage is responsible for accessing memory, either to load or store data, as required by the instruction.

  18. Question 18

    Q18. Which of the following is a type of parallelism that involves executing multiple threads or processes simultaneously?

    • A) Instruction-level parallelism
    • B) Thread-level parallelism
    • C) Data parallelism
    • D) Pipelining

    Answer: Thread-level parallelism

    Explanation: Thread-level parallelism involves executing multiple threads or processes simultaneously, improving overall system utilization and throughput.

  19. Question 19

    Q19. What is the main benefit of using a 'write-through' cache policy?

    • A) Improved cache hit ratio
    • B) Reduced cache miss penalty
    • C) Simplified cache coherence
    • D) Faster write operations

    Answer: Simplified cache coherence

    Explanation: Write-through cache policy ensures that data is written to both the cache and main memory, simplifying cache coherence and reducing the risk of data inconsistency.

  20. Question 20

    Q20. Which bus is responsible for transferring data between the CPU and memory?

    • A) Control Bus
    • B) Address Bus
    • C) Data Bus
    • D) Interrupt Bus

    Answer: Data Bus

    Explanation: The Data Bus transfers data between the CPU and memory or I/O devices, facilitating data exchange.