Bahria University Entry Test computer science Computer Architecture — Set 3

Computer Architecture MCQs set 3 for Bahria University Entry Test computer science — 20 solved questions.

Bahria University Entry Test computer science Computer Architecture — Set 3

  1. Question 1

    Q1. What is the term for a CPU design that uses a single pipeline for instruction execution?

    • A) Superscalar
    • B) Pipelining
    • C) Multicore
    • D) Scalar

    Answer: Pipelining

    Explanation: Pipelining is a technique where instructions are processed in a linear sequence of stages, improving instruction throughput.

  2. Question 2

    Q2. In a cache memory system, what is the term for a cache miss that occurs when the requested data is not in the cache?

    • A) Compulsory Miss
    • B) Capacity Miss
    • C) Conflict Miss
    • D) Cache Hit

    Answer: Compulsory Miss

    Explanation: A compulsory miss occurs when the data is accessed for the first time, and it's not in the cache.

  3. Question 3

    Q3. What is the primary advantage of using a Harvard Architecture?

    • A) Improved instruction-level parallelism
    • B) Increased cache size
    • C) Separate instruction and data buses
    • D) Reduced power consumption

    Answer: Separate instruction and data buses

    Explanation: Harvard Architecture uses separate buses for instructions and data, improving bandwidth and reducing contention.

  4. Question 4

    Q4. What is the term for the technique of increasing the clock speed of a CPU by using multiple processing stages?

    • A) Pipelining
    • B) Multithreading
    • C) Overclocking
    • D) Hyper-threading

    Answer: Pipelining

    Explanation: Pipelining breaks down instruction execution into stages, allowing for increased clock speeds.

  5. Question 5

    Q5. In a virtual memory system, what is the term for the mapping of virtual addresses to physical addresses?

    • A) Paging
    • B) Segmentation
    • C) Address Translation
    • D) Memory Management

    Answer: Address Translation

    Explanation: Address Translation maps virtual addresses to physical addresses using page tables or segment tables.

  6. Question 6

    Q6. Which of the following cache replacement policies replaces the least recently used cache line?

    • A) LRU (Least Recently Used)
    • B) FIFO (First-In-First-Out)
    • C) Random Replacement
    • D) Optimal Replacement

    Answer: LRU (Least Recently Used)

    Explanation: LRU replaces the cache line that has not been accessed for the longest time, reducing cache misses.

  7. Question 7

    Q7. What is the term for a CPU that can execute multiple instructions in a single clock cycle?

    • A) Superscalar
    • B) Pipelined
    • C) Multicore
    • D) Multithreaded

    Answer: Superscalar

    Explanation: Superscalar CPUs execute multiple instructions in parallel, improving instruction-level parallelism. NET computer science MCQs often test this core concept.

  8. Question 8

    Q8. In a DMA (Direct Memory Access) transfer, what is the role of the DMA controller?

    • A) To transfer data between I/O devices and memory
    • B) To manage the CPU's instruction pipeline
    • C) To handle interrupts
    • D) To manage the cache hierarchy

    Answer: To transfer data between I/O devices and memory

    Explanation: The DMA controller manages data transfer between I/O devices and memory, offloading the CPU.

  9. Question 9

    Q9. What is the primary advantage of using a multi-core processor?

    • A) Improved single-thread performance
    • B) Increased instruction-level parallelism
    • C) Enhanced multithreading capabilities
    • D) Reduced power consumption

    Answer: Enhanced multithreading capabilities

    Explanation: Multi-core processors provide multiple execution cores, enabling concurrent execution of multiple threads.

  10. Question 10

    Q10. What is the term for the process of predicting the outcome of a branch instruction?

    • A) Branch Prediction
    • B) Instruction Pre-fetch
    • C) Cache Pre-fetch
    • D) Speculative Execution

    Answer: Branch Prediction

    Explanation: Branch Prediction predicts the outcome of branch instructions, reducing branch penalties. NET computer science MCQs often test this core concept.

  11. Question 11

    Q11. In a computer system, what is the function of the Interrupt Controller?

    • A) To manage the CPU's instruction pipeline
    • B) To handle interrupts from I/O devices
    • C) To manage the cache hierarchy
    • D) To transfer data between I/O devices and memory

    Answer: To handle interrupts from I/O devices

    Explanation: The Interrupt Controller prioritizes and handles interrupts from I/O devices, notifying the CPU.

  12. Question 12

    Q12. What is the term for the technique of executing instructions speculatively, before the branch outcome is known?

    • A) Speculative Execution
    • B) Branch Prediction
    • C) Instruction Pre-fetch
    • D) Cache Pre-fetch

    Answer: Speculative Execution

    Explanation: Speculative Execution executes instructions before the branch outcome is known, improving instruction-level parallelism.

  13. Question 13

    Q13. In a pipelined CPU, what is the term for a situation where an instruction depends on the result of a previous instruction?

    • A) Data Hazard
    • B) Control Hazard
    • C) Structural Hazard
    • D) Pipeline Stall

    Answer: Data Hazard

    Explanation: Data Hazards occur when an instruction depends on the result of a previous instruction, requiring data forwarding or stalls.

  14. Question 14

    Q14. Which of the following cache mapping techniques uses a tag to identify the cache line?

    • A) Direct mapping
    • B) Associative mapping
    • C) Set-associative mapping
    • D) All of the above

    Answer: All of the above

    Explanation: All three techniques use tags to identify cache lines, though they differ in how they map main memory to cache.

  15. Question 15

    Q15. What is the hit ratio of a cache memory if the cache access time is 10 ns and main memory access time is 100 ns, and the effective access time is 15 ns?

    • A) 0.85
    • B) 0.9
    • C) 0.95
    • D) 0.98

    Answer: 0.95

    Explanation: Using the formula: Effective Access Time = Hit Ratio * Cache Access Time + (1 - Hit Ratio) * Main Memory Access Time, we can solve for Hit Ratio.

  16. Question 16

    Q16. In a pipelined processor, what is the primary cause of pipeline stalls?

    • A) Cache misses
    • B) Branch instructions
    • C) Data dependencies
    • D) All of the above

    Answer: All of the above

    Explanation: Pipeline stalls occur due to cache misses, branch mispredictions, and data dependencies, as they disrupt the smooth flow of instructions.

  17. Question 17

    Q17. In a 2-level cache hierarchy, what is the purpose of the L2 cache?

    • A) To act as a buffer between the CPU and main memory
    • B) To store frequently accessed instructions
    • C) To reduce the access time to main memory
    • D) To increase the hit ratio of the L1 cache

    Answer: To reduce the access time to main memory

    Explanation: The L2 cache acts as a secondary cache, reducing the access time to main memory by storing data that is not in the L1 cache.

  18. Question 18

    Q18. What is the function of the Memory Address Register (MAR) in a CPU?

    • A) To store the data being transferred
    • B) To store the memory address
    • C) To store the instruction being executed
    • D) To store the program counter

    Answer: To store the memory address

    Explanation: The MAR holds the memory address of the data being accessed. NET computer science MCQs often test this core concept.

  19. Question 19

    Q19. In a CPU, what is the function of the Arithmetic Logic Unit (ALU)?

    • A) To perform arithmetic and logical operations
    • B) To store data temporarily
    • C) To control the flow of data
    • D) To manage memory access

    Answer: To perform arithmetic and logical operations

    Explanation: The ALU performs arithmetic and logical operations on data, such as addition, subtraction, and bitwise operations.

  20. Question 20

    Q20. What is the main advantage of using a cache memory?

    • A) Increased memory capacity
    • B) Improved security
    • C) Reduced average memory access time
    • D) Simplified design

    Answer: Reduced average memory access time

    Explanation: Cache memory reduces the average memory access time by storing frequently accessed data in a faster, more accessible location.