engineering computer science MCQ #53

In a pipelined CPU, what is the term for a situation where an instruction depends on the result of a previous instruction?

engineering computer science MCQ #53

  1. Question 1

    Q1. In a pipelined CPU, what is the term for a situation where an instruction depends on the result of a previous instruction?

    • A) Data Hazard
    • B) Control Hazard
    • C) Structural Hazard
    • D) Pipeline Stall

    Answer: Data Hazard

    Explanation: Data Hazards occur when an instruction depends on the result of a previous instruction, requiring data forwarding or stalls.