NTS NAT-ICS (Computer Science Track) Computer Science: Practice MCQs with Answers

NTS NAT-ICS (Computer Science Track) Computer Science Practice sample MCQs

1. Q1. What is the CRC for the data 1010 with a divisor of 1011?

   • A) 011
   • B) 110
   • C) 101
   • D) 001

   Answer: 011

2. Q2. What is the output of the expression 2 + 3 * 4?

   • A) 20
   • B) 14
   • C) 11
   • D) 24

   Answer: 14

3. Q3. What is the result of the expression: 12 % 5?

   • A) 2
   • B) 2.4
   • C) 3
   • D) 4

   Answer: 2

4. Q4. Which operator is used for bitwise XOR?

   • A) &
   • B) |
   • C) ^
   • D) ~

   Answer: ^

5. Q5. What is the value of: 5 & 3

   • A) 1
   • B) 3
   • C) 5
   • D) 7

   Answer: 1

6. Q6. What is the primary function of the Instruction Register (IR)?

   • A) To store the address of the next instruction
   • B) To store the current instruction being executed
   • C) To store the result of an operation
   • D) To store the data being transferred

   Answer: To store the current instruction being executed

7. Q7. Which cache mapping technique maps a block to a specific cache line?

   • A) Direct Mapping
   • B) Associative Mapping
   • C) Set-Associative Mapping
   • D) None of the above

   Answer: Direct Mapping

8. Q8. What is the hit ratio if 80 out of 100 memory accesses are found in the cache?

   • A) 0.2
   • B) 0.8
   • C) 0.5
   • D) 0.1

   Answer: 0.8

9. Q9. A CPU has a clock cycle time of 2 ns. What is the clock speed?

   • A) 500 MHz
   • B) 1 GHz
   • C) 2 GHz
   • D) 4 GHz

   Answer: 1 GHz

10. Q10. What is the main advantage of a pipelined processor?

    • A) Increased instruction-level parallelism
    • B) Reduced instruction execution time
    • C) Improved branch prediction
    • D) Simplified instruction decoding

    Answer: Increased instruction-level parallelism

11. Q11. A computer system has 4GB of RAM. What is the minimum number of bits required to address each byte?

    • A) 32
    • B) 31
    • C) 30
    • D) 29

    Answer: 32

12. Q12. What is the primary function of the Program Counter (PC)?

    • A) To store the current instruction
    • B) To store the address of the next instruction
    • C) To store the result of an operation
    • D) To store the data being transferred

    Answer: To store the address of the next instruction

13. Q13. Which of the following is a type of cache coherence protocol?

    • A) MESI
    • B) FIFO
    • C) LRU
    • D) None of the above

    Answer: MESI

14. Q14. What is the main disadvantage of a direct-mapped cache?

    • A) High cost
    • B) Low hit ratio
    • C) Conflict misses
    • D) None of the above

    Answer: Conflict misses

15. Q15. A processor has a 5-stage pipeline. What is the maximum speedup achievable?

    • A) 2
    • B) 5
    • C) 10
    • D) None of the above

    Answer: 5

16. Q16. A computer system has a 2-way set-associative cache. What is the main advantage?

    • A) Reduced conflict misses
    • B) Improved hit ratio
    • C) Increased cache size
    • D) None of the above

    Answer: Reduced conflict misses

17. Q17. Which of the following is a type of parallelism?

    • A) Instruction-level parallelism
    • B) Data-level parallelism
    • C) Thread-level parallelism
    • D) All of the above

    Answer: All of the above

18. Q18. A processor has a clock speed of 2 GHz. What is the clock cycle time?

    • A) 0.5 ns
    • B) 1 ns
    • C) 2 ns
    • D) None of the above

    Answer: 0.5 ns

19. Q19. What is the Hamming distance between 1001 and 1101?

    • A) 1
    • B) 2
    • C) 3
    • D) 4

    Answer: 1

20. Q20. What is the output of `printf('%d', sizeof(char));`?

    • A) 1
    • B) 2
    • C) 4
    • D) Depends on the system

    Answer: 1

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