PU CET Lahore (Engineering & CS) Computer Science: Most Repeated MCQs with Answers

PU CET Lahore (Engineering & CS) Computer Science Most Repeated sample MCQs

1. Q1. What is the Hamming distance between 1001 and 1101?

   • A) 1
   • B) 2
   • C) 3
   • D) 4

   Answer: 1

2. Q2. What is the output of `printf('%d', sizeof(char));`?

   • A) 1
   • B) 2
   • C) 4
   • D) Depends on the system

   Answer: 1

3. Q3. What is the main advantage of using a Harvard architecture over a von Neumann architecture?

   • A) Simplified instruction decoding
   • B) Faster execution due to separate instruction and data buses
   • C) Improved memory utilization
   • D) Reduced CPU complexity

   Answer: Faster execution due to separate instruction and data buses

4. Q4. In a pipelined processor, what is the primary function of the 'IF' stage?

   • A) Instruction Fetch
   • B) Instruction Decode
   • C) Execution
   • D) Memory Access

   Answer: Instruction Fetch

5. Q5. What is the purpose of the 'TLB' in a virtual memory system?

   • A) To cache frequently accessed instructions
   • B) To cache frequently accessed data
   • C) To cache page tables
   • D) To cache translation of virtual to physical addresses

   Answer: To cache translation of virtual to physical addresses

6. Q6. What is the main benefit of out-of-order execution in a processor?

   • A) Improved instruction-level parallelism
   • B) Simplified instruction decoding
   • C) Reduced power consumption
   • D) Increased cache hits

   Answer: Improved instruction-level parallelism

7. Q7. Which of the following cache replacement policies is based on the least recently used block?

   • A) FIFO
   • B) LRU
   • C) Random
   • D) Optimal

   Answer: LRU

8. Q8. What is the primary function of the 'ID' stage in a pipelined processor?

   • A) Instruction Fetch
   • B) Instruction Decode
   • C) Execution
   • D) Memory Access

   Answer: Instruction Decode

9. Q9. In a virtual memory system, what is the purpose of the 'page table'?

   • A) To store the page frames in main memory
   • B) To store the mapping of virtual to physical addresses
   • C) To store the page replacement policy
   • D) To store the page fault handler

   Answer: To store the mapping of virtual to physical addresses

10. Q10. What is the main advantage of using a multi-core processor?

    • A) Improved single-threaded performance
    • B) Increased instruction-level parallelism
    • C) Better multithreading support
    • D) Reduced power consumption

    Answer: Better multithreading support

11. Q11. Which of the following is a characteristic of a CISC (Complex Instruction Set Computer) architecture?

    • A) Load/store architecture
    • B) Simple instruction set
    • C) Microcode-based instruction execution
    • D) Fixed-length instructions

    Answer: Microcode-based instruction execution

12. Q12. What is the purpose of the 'branch predictor' in a processor?

    • A) To predict the outcome of a branch instruction
    • B) To predict the target address of a branch instruction
    • C) To predict the instruction fetch sequence
    • D) To predict the data access pattern

    Answer: To predict the outcome of a branch instruction

13. Q13. In a pipelined processor, what is the effect of a 'stall' or 'bubble'?

    • A) It increases the instruction-level parallelism
    • B) It reduces the instruction-level parallelism
    • C) It improves the branch prediction accuracy
    • D) It reduces the cache miss rate

    Answer: It reduces the instruction-level parallelism

14. Q14. What is the primary function of the 'MEM' stage in a pipelined processor?

    • A) Instruction Fetch
    • B) Instruction Decode
    • C) Execution
    • D) Memory Access

    Answer: Memory Access

15. Q15. Which of the following is a type of parallelism that involves executing multiple threads or processes simultaneously?

    • A) Instruction-level parallelism
    • B) Thread-level parallelism
    • C) Data parallelism
    • D) Pipelining

    Answer: Thread-level parallelism

16. Q16. What is the main benefit of using a 'write-through' cache policy?

    • A) Improved cache hit ratio
    • B) Reduced cache miss penalty
    • C) Simplified cache coherence
    • D) Faster write operations

    Answer: Simplified cache coherence

17. Q17. Which bus is responsible for transferring data between the CPU and memory?

    • A) Control Bus
    • B) Address Bus
    • C) Data Bus
    • D) Interrupt Bus

    Answer: Data Bus

18. Q18. What is the term for a CPU design that uses a single pipeline for instruction execution?

    • A) Superscalar
    • B) Pipelining
    • C) Multicore
    • D) Scalar

    Answer: Pipelining

19. Q19. In a cache memory system, what is the term for a cache miss that occurs when the requested data is not in the cache?

    • A) Compulsory Miss
    • B) Capacity Miss
    • C) Conflict Miss
    • D) Cache Hit

    Answer: Compulsory Miss

20. Q20. What is the primary advantage of using a Harvard Architecture?

    • A) Improved instruction-level parallelism
    • B) Increased cache size
    • C) Separate instruction and data buses
    • D) Reduced power consumption

    Answer: Separate instruction and data buses

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