PU CET Lahore (Engineering & CS) Computer Science: Past Papers MCQs with Answers

PU CET Lahore (Engineering & CS) Computer Science Past Papers sample MCQs

1. Q1. What is the CRC for the data 1010 with a divisor of 1011?

   • A) 011
   • B) 110
   • C) 101
   • D) 001

   Answer: 011

2. Q2. What is the result of the expression: 12 % 5?

   • A) 2
   • B) 2.4
   • C) 3
   • D) 4

   Answer: 2

3. Q3. What is the value of: 5 & 3

   • A) 1
   • B) 3
   • C) 5
   • D) 7

   Answer: 1

4. Q4. A cache memory has a size of 256 KB, block size of 64 bytes. How many blocks?

   • A) 4096
   • B) 2048
   • C) 1024
   • D) 512

   Answer: 4096

5. Q5. In a computer system, what is the function of the Interrupt Controller?

   • A) To manage the CPU's instruction pipeline
   • B) To handle interrupts from I/O devices
   • C) To manage the cache hierarchy
   • D) To transfer data between I/O devices and memory

   Answer: To handle interrupts from I/O devices

6. Q6. What is the term for the technique of executing instructions speculatively, before the branch outcome is known?

   • A) Speculative Execution
   • B) Branch Prediction
   • C) Instruction Pre-fetch
   • D) Cache Pre-fetch

   Answer: Speculative Execution

7. Q7. In a pipelined CPU, what is the term for a situation where an instruction depends on the result of a previous instruction?

   • A) Data Hazard
   • B) Control Hazard
   • C) Structural Hazard
   • D) Pipeline Stall

   Answer: Data Hazard

8. Q8. Which of the following cache mapping techniques uses a tag to identify the cache line?

   • A) Direct mapping
   • B) Associative mapping
   • C) Set-associative mapping
   • D) All of the above

   Answer: All of the above

9. Q9. What is the hit ratio of a cache memory if the cache access time is 10 ns and main memory access time is 100 ns, and the effective access time is 15 ns?

   • A) 0.85
   • B) 0.9
   • C) 0.95
   • D) 0.98

   Answer: 0.95

10. Q10. In a pipelined processor, what is the primary cause of pipeline stalls?

    • A) Cache misses
    • B) Branch instructions
    • C) Data dependencies
    • D) All of the above

    Answer: All of the above

11. Q11. In a 2-level cache hierarchy, what is the purpose of the L2 cache?

    • A) To act as a buffer between the CPU and main memory
    • B) To store frequently accessed instructions
    • C) To reduce the access time to main memory
    • D) To increase the hit ratio of the L1 cache

    Answer: To reduce the access time to main memory

12. Q12. In a CPU, what is the function of the Arithmetic Logic Unit (ALU)?

    • A) To perform arithmetic and logical operations
    • B) To store data temporarily
    • C) To control the flow of data
    • D) To manage memory access

    Answer: To perform arithmetic and logical operations

13. Q13. What is the main advantage of using a cache memory?

    • A) Increased memory capacity
    • B) Improved security
    • C) Reduced average memory access time
    • D) Simplified design

    Answer: Reduced average memory access time

14. Q14. In a pipelined processor, what is the purpose of the instruction pipeline?

    • A) To store instructions in a buffer
    • B) To decode instructions
    • C) To execute instructions in a sequence of stages
    • D) To manage memory access

    Answer: To execute instructions in a sequence of stages

15. Q15. What is the function of the Status Register in a CPU?

    • A) To store the program counter
    • B) To store the current instruction being executed
    • C) To store the status flags
    • D) To store the data being processed

    Answer: To store the status flags

16. Q16. Which of the following is a type of cache replacement policy?

    • A) FIFO
    • B) LRU
    • C) Random
    • D) All of the above

    Answer: All of the above

17. Q17. What is the primary function of the Control Unit in a CPU?

    • A) To perform arithmetic and logical operations
    • B) To manage memory access
    • C) To control the flow of data and instructions
    • D) To store data temporarily

    Answer: To control the flow of data and instructions

18. Q18. What is the main difference between a Microprocessor and a Microcontroller?

    • A) Number of pins
    • B) Clock speed
    • C) Presence of on-chip memory and peripherals
    • D) Instruction set architecture

    Answer: Presence of on-chip memory and peripherals

19. Q19. In a CPU, what is the function of the Bus?

    • A) To store data temporarily
    • B) To manage memory access
    • C) To transfer data between components
    • D) To control the flow of data

    Answer: To transfer data between components

20. Q20. What is the purpose of the Interrupt Handling mechanism in a CPU?

    • A) To handle exceptions and interrupts
    • B) To manage memory access
    • C) To control the flow of data
    • D) To store data temporarily

    Answer: To handle exceptions and interrupts

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