A CPU has a 4-stage pipeline. What is the maximum number of instructions that can be executed in 8 clock cycles?
Q1. A CPU has a 4-stage pipeline. What is the maximum number of instructions that can be executed in 8 clock cycles?
Answer: 8
Explanation: In a 4-stage pipeline, one instruction is completed every clock cycle after the initial 4-cycle latency, so 8 cycles can execute 8 - (4-1) = 5 instructions, but considering the pipeline filling, it can be 8 instructions in 8 cycles if we consider the steady state.