engineering computer science MCQ #104

A CPU has a 5-stage pipeline. If it takes 2 clock cycles to fetch data, what is the maximum throughput?

engineering computer science MCQ #104

  1. Question 1

    Q1. A CPU has a 5-stage pipeline. If it takes 2 clock cycles to fetch data, what is the maximum throughput?

    • A) 1/5 instructions per cycle
    • B) 1/2 instructions per cycle
    • C) 1 instruction per cycle
    • D) 2 instructions per cycle

    Answer: 1 instruction per cycle

    Explanation: In a pipelined CPU, maximum throughput is achieved when the pipeline is full. Here, it's 1 instruction per cycle as each stage takes 1 cycle.