engineering computer science MCQ #126

In a 2-level cache hierarchy, L1 cache has an access time of 1 cycle and a miss rate of 0.05. L2 cache has an access time of 5 cycles and a miss rate of 0.02. What is the average memory access time?

engineering computer science MCQ #126

  1. Question 1

    Q1. In a 2-level cache hierarchy, L1 cache has an access time of 1 cycle and a miss rate of 0.05. L2 cache has an access time of 5 cycles and a miss rate of 0.02. What is the average memory access time?

    • A) 1 + (0.05 * 5)
    • B) 1 + (0.05 * (5 + (0.02 * 100)))
    • C) 1 + (0.05 * 5) + (0.05 * 0.02 * 100)
    • D) 1 + (0.05 * (5 + 0.02))

    Answer: 1 + (0.05 * (5 + (0.02 * 100)))

    Explanation: Average memory access time = L1 access time + (L1 miss rate * (L2 access time + (L2 miss rate * main memory access time))).