engineering computer science MCQ #173

A pipelined processor has 4 stages, each taking 1 clock cycle. What is the ideal speedup?

engineering computer science MCQ #173

  1. Question 1

    Q1. A pipelined processor has 4 stages, each taking 1 clock cycle. What is the ideal speedup?

    • A) 2
    • B) 4
    • C) 1
    • D) 3

    Answer: 4

    Explanation: Ideal speedup = number of stages = 4, as the pipeline can process 4 instructions simultaneously.