engineering computer science MCQ #183

In a 2-level cache hierarchy, L1 cache access time is 1 cycle and L2 cache access time is 5 cycles. If L1 hit rate is 80% and L2 hit rate is 90%, what is the average memory access time?

engineering computer science MCQ #183

  1. Question 1

    Q1. In a 2-level cache hierarchy, L1 cache access time is 1 cycle and L2 cache access time is 5 cycles. If L1 hit rate is 80% and L2 hit rate is 90%, what is the average memory access time?

    • A) 2 cycles
    • B) 2.2 cycles
    • C) 2.5 cycles
    • D) 3 cycles

    Answer: 2.2 cycles

    Explanation: Average memory access time = L1 hit time + L1 miss rate * (L2 hit time + L2 miss rate * main memory access time), assuming main memory access time as very high, the equation simplifies to 1 + 0.2 * (5 + 0.1 * main memory access.