engineering computer science MCQ #215

In a pipelined CPU, what is a pipeline stall?

engineering computer science MCQ #215

  1. Question 1

    Q1. In a pipelined CPU, what is a pipeline stall?

    • A) A situation where the pipeline is fully utilized
    • B) A situation where the pipeline is idle due to a dependency
    • C) A situation where the pipeline is executing instructions out of order
    • D) A situation where the pipeline is executing instructions in order

    Answer: A situation where the pipeline is idle due to a dependency

    Explanation: A pipeline stall occurs when the pipeline is idle due to a dependency, such as a data hazard or a branch misprediction, which prevents the next instruction from being executed.