engineering computer science MCQ #239

A computer has a 4-stage pipeline. If the stages take 2, 3, 1, and 4 clock cycles respectively, what is the maximum clock rate?

engineering computer science MCQ #239

  1. Question 1

    Q1. A computer has a 4-stage pipeline. If the stages take 2, 3, 1, and 4 clock cycles respectively, what is the maximum clock rate?

    • A) 1 / 4 GHz
    • B) 1 / 3 GHz
    • C) 1 / 2 GHz
    • D) 1 / 10 GHz

    Answer: 1 / 2 GHz

    Explanation: Maximum clock rate is determined by the slowest stage, which is 4 cycles, so clock rate = 1 / max(stage times) = 1 / 4 = 0.25 GHz or 1 / 4 GHz.