A CPU has a 5-stage pipeline. What is the maximum number of instructions that can be executed in 10 clock cycles?
Q1. A CPU has a 5-stage pipeline. What is the maximum number of instructions that can be executed in 10 clock cycles?
Answer: 10
Explanation: In a 5-stage pipeline, one instruction is completed every clock cycle after the initial 5-cycle latency, so 10 cycles can execute 10 - (5-1) = 6 instructions, but considering the pipeline filling, it can be 10 instructions in 10 cycles if we consider the steady state.